1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to a method of manufacturing a chip size package. The chip size package (CSP) generally refers to a package which has a size approximately equal to or slightly larger than a chip size, and intends high-density mounting on the printed(/circuit) board. The present invention relates to technology for improving reliability of the formation of a metal post adopted for the CSP.
2. Description of the Related Art
In this technical field, previously known are a structure called xe2x80x9cBGA (Ball Grid Array)xe2x80x9d having a plurality of solder balls arranged in a plane, a structure called xe2x80x9cfine pitch BGAxe2x80x9d in which the ball pitch of the BGA is further decreased to reduce the external shape to a chip size, etc.
In recent years, a wafer CSP has been proposed in xe2x80x9cNIKKEI MICRODEVICExe2x80x9d August, 1998, pp 44-71. This wafer CSP is a CSP in which wirings and pads in an array are basically formed in a wafer process (pre-step) before chip dicing. This technique is expected that it can integrate the wafer process and package process (post-step) to reduce package cost greatly.
The wafer CSP is classified into a resin-sealing type and a rearrangement wiring type (hereinafter referred to as rewiring type). The resin sealing type has a structure with the surface covered with sealing resin like a conventional package, in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is sealed with sealing resin.
Generally, it is said that when a package is loaded on a printed board, the stress generated owing to a difference in their thermal expansion coefficient therebetween is concentrated to the metal posts, but the resin sealing type, which has the metal posts with an increased length, can disperse the stress.
On the other hand, the rewiring type has a structure in which rewiring is made without using sealing resin as shown in FIG. 10. Specifically, an Al electrode 52, a wiring layer 53 and an insulating layer 54 are stacked on the surface of a chip 51, and a metal post 55 is formed on the wiring layer 53. A solder ball is formed on the metal post 56. The wiring layer 53 is used as a rewiring for arranging the solder ball 56 in a prescribed array on the chip.
The resin sealing type in which the metal post with a length increased to about 100 xcexcm is reinforced by sealing resin can acquire great reliability. However, the process of resin sealing using a transfer molding must be carried out using a old. This complicates the manufacturing process.
On the other hand, the rewiring type has an advantage that the manufacturing process is relatively simple and most steps thereof can be performed in a wafer process. However, any means is required to relax the stress by any technique to enhance the reliability.
Where an Al electrode is used, at least one layer of barrier metal (not shown) is formed between the metal post 55 and Al electrode 52, and the solder ball 56 is formed on the metal post 55.
The wafer CSP described above is sealed using e.g. epoxy resin. In this case, the epoxy resin layer is polished to expose the head of the metal post. This step is succeeded by a dicing step. In such a process, the wafer will greatly warp owing to the stress applied to the wafer and resin.
Where the wafer subjected to such warp is transported in a manufacturing line, a transporting error occurred sometimes. This was remarkable as the diameter of the wafer increases.
The problem of warping is also hindrance when height of the metal post is increased in order to enhance the reliability.
The present invention has been accomplished under the above circumstance.
An object of the invention is to provide a semiconductor device which can prevent warp of a wafer and give great reliability.
In order to attain the above object, in accordance with the invention, there is provided a method of manufacturing a semiconductor device comprising the steps: preparing a semiconductor wafer having a wiring layer for external connection and a dicing groove having a prescribed depth; covering an upper surface of the semiconductor wafer with a resin layer; grinding the semiconductor wafer from its lower surface to the bottom of the groove; grinding the resin layer to expose the head of the wiring layer; and forming an external connection terminal to the exposed head.
The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.